1. Field of the Invention
This invention relates to an asynchronous transfer mode (ATM) cell switching apparatus for exchanging cells at a high speed which are obtained from various information for multimedia, such as voices, data and images, in blocks.
2. Prior Art
FIG. 1 is a block diagram showing a conventional ATM cell exchanging apparatus disclosed in Japanese Patent Disclosure No. 117241/90, for example. In FIG. 1, the reference numerals 1.sub.1 -1.sub.n designate n (n.gtoreq.2) input lines through which packets are input. Each packet has a fixed length and has a header portion including encoded destination information. 2.sub.1 -2.sub.m designate m (m.gtoreq.2) output lines through which the packets are output depending on the destinations specified by the header portions. 3.sub.1 -3.sub.l designate l (l.gtoreq.n) buffer memories in which the input packets are temporarily stored. 4 designates an empty buffer selection switch for connecting each of the input lines (i.e., wire, channel, or bus) 1.sub.1 -1.sub.n, through which a packet is input, to an empty one of the buffer memories 3.sub.1 -3.sub.l.
Each of the buffer memories 3.sub.1 -3.sub.l has a corresponding header memory circuit (5.sub.1 -5.sub.l) for extracting and storing only the header portions of those packets which are stored in the corresponding buffer memories. Outgoing line selection circuits 6.sub.1 -6.sub.l are provided, each corresponding to one of the header memory circuits 5.sub.1 -5.sub.l for making the outputs thereof significant, i.e., "1", from which the stored contents of the corresponding header memory circuits are sent to output lines.
Each of the output lines 2.sub.1 -2.sub.m has a corresponding encoder 7.sub.1 -7.sub.m for receiving outputs from the output selection circuits 6.sub.1 -6.sub.l to encode the outputs as buffer numbers of the buffer memories 3.sub.1 -3.sub.l. First-in, first-out type (hereinafter referred to FIFO) memories 8.sub.1 -8.sub.m are provided, each having a corresponding encoder 7.sub.1 -7.sub.m such that the buffer numbers encoded by the encoders 7.sub.1 -7.sub.m are written into the corresponding FIFO memories and then read out therefrom in the same order that the buffer numbers are input. 9.sub.1 -9.sub.m are buffer connection switches controlled in accordance with the buffer numbers delivered from the corresponding FIFO memories for outputting the packets stored in the buffer memories to the output lines specified by the header portions of the packets.
Although the packet is used here instead of an ATM cell to describe a transmitted unit of information, both the terms ATM cell and "packet" mean the same thing in that multimedia information is divided into blocks and a header including destination information is added to each block. Generally, however, the two terms are different in that the packet is handled as having blocks of variable length, while the ATM cell is handled as having a fixed length prescribed by CCITT recommendation 1.113 (1988) which deals with asynchronous transfer mode systems.
Operation of a conventional ATM cell exchanging apparatus will now be described. FIG. 2 is a time chart showing a timing relation between signals at the various points. This figure illustrates control flow for receiving, at the same time, packets sent from the input lines 1.sub.1 and 1.sub.n to the output line 2.sub.1 when the buffer memories 3.sub.1 and 3.sub.l are empty. It is also assumed that the packets handled here have a fixed length as mentioned above and the header portions include, as destination information, encoded output line numbers.
When a packet arrives through any one of the input lines 1.sub.1 -1.sub.n, the empty buffer selection switch 4 selects an empty one of the buffer memories 3.sub.1 -3.sub.l and connects it to the input line along which the packet has arrived. Here, if two packets, having the same output line number "1", and designating the output line 2.sub.1, arrive through the input lines 1.sub.1 and 1.sub.n at the same time, as shown in FIGS. 2(a) and 2(b), the empty buffer selection switch 4 selects the input lines 1.sub.1 -1.sub.n and the buffer memories 3.sub.1 -3.sub.l one by one in ascending order, for example, and interconnects a selected pair of the input line and the buffer memory. In this case, therefore, the empty buffer selection switch 4 connects the input line 1.sub.1 to the buffer memory 3.sub.1 and the input line 1.sub.n to the buffer memory 3.sub.l, whereby a packet A having arrived along the input line 1.sub.1 is stored in the buffer memory 3.sub.1 and a packet B having arrived along the input line 1.sub.n is stored in the buffer memory 3.sub.l, respectively.
With the switching operation of the empty buffer selection switch 4, the packet A is also supplied to the header memory circuit 5.sub.1 corresponding to the buffer memory 3.sub.1 and the packet B is supplied to the header memory circuit 5.sub.l corresponding to the buffer memory 3.sub.l. The header memory circuits 5.sub.1 -5.sub.l serve to extract only the header portions of the received packets and to store the contents of the header portions, i.e., the output line numbers. Accordingly, the output line number "1" designating the output line 2.sub.1 is stored in the header memory circuits 5.sub.1 and 5.sub.l. The contents of the header memory circuits 5.sub.1 and 5.sub.l are sent to the corresponding output line selection circuits 6.sub.1 and 6.sub.l, respectively. Among the outputs of the output line selection circuit 6.sub.1 -6.sub.l, those outputs which identify the output lines corresponding to the output line numbers specified by the contents of the header memory circuits turn to a significant level, that is, "1", and outputs which identify other output lines remain insignificant, i.e., "0".
Accordingly, the output line selection circuit 6.sub.1 sets the output to the encoder 7.sub.1 to "1" as shown in FIG. 2(c), and the output line selection circuit 6.sub.l also sets the output to the encoder 7.sub.1 to "1" as shown in FIG. 2(d). When any one of the outputs of the output line selection circuits 6.sub.1 -6.sub.l is turned to "1", its corresponding encoder (one of 7.sub.1 -7.sub.m) encodes the buffer number of the buffer memory the output line selection circuit, and causes the encoded buffer number to be stored in the corresponding FIFO memory (one of 8.sub.1 -8.sub.m). When the output of the two output line selection circuits 6.sub.1 and 6.sub.l turn to "1" at the same time as shown in FIGS. 2(c) and 2(d), the encoder 7.sub.1 causes the buffer numbers to be stored in the FIFO memory in ascending order, for example.
Therefore, the FIFO memory 8.sub.1 first stores the buffer number 1 of the buffer memory 3.sub.1 and then stores the buffer number l of the buffer memory 3.sub.l. Each of the buffer connection switches 9.sub.1 -9.sub.m reads out the buffer numbers, stored in the FIFO memories 8.sub.1 -8.sub.m, in the order of the buffer numbers stored, and connects the buffer memories designated by the read-out buffer numbers to the output line connected to the buffer connection switch.
Specifically, as shown in FIG. 2(e), the buffer connection switch 9.sub.1 first reads the buffer number 1 out of the FIFO memory 8.sub.1 and, after the completion of the necessary connection process, reads the next buffer number l therefrom. When the buffer number 1 is read out, the buffer memory 3.sub.1 is connected to the output line 2.sub.1 and the packet A stored in the buffer memory 3.sub.1 is output to the output line 2.sub.1 as shown in FIG. 2(f). After the completion of outputting the packet A to the output line 2.sub.1, the buffer number l is read out as mentioned above, whereupon the buffer memory 3.sub.l is connected to the output line 2.sub.1 and the packet B stored in the buffer memory 3.sub.l is output to the output line 2.sub.1, as shown in FIG. 2(g). As a result, the packets A and B are output to the output line 2.sub.1, successively, as shown in FIG. 2(h).
Whenever a packet is delivered to one of the outgoing line 2.sub.1 -2.sub.m, the buffer connection switches 9.sub.1 -9.sub.m release a corresponding one of the buffer memories 3.sub.1 -3.sub.l and inform the empty buffer selection switch 4 of that fact so as to make it ready for receiving further packets.
In the conventional ATM cell exchanging apparatus, only one ATM cell can be stored in each of the buffer memories 3.sub.1 -3.sub.l thus avoiding any collision between ATM cells (packets) when the ATM cells are read out of the buffer memories. If the number of ATM cells to be written exceeds the number of buffer memories 3.sub.1 -3.sub.l, the excessive ATM cells are discarded. To reduce the number of discarded ATM cells, a large quantity of buffer memories is required. This necessarily increases the size of the empty buffer selection switch 4 for connecting the input lines to the buffer memories and the buffer connection switches for connecting the buffer memories to the output lines 2.sub.1 -2.sub.m.